Advanced logic synthesis
This book provides a single-source reference to the state-of-the-art in logic synthesis. Readers will benefit from the authors' expert perspectives on new technologies and logic synthesis, new data structures, big data and logic synthesis, and convergent logic synthesis. The authors describe te...
| Other Authors: | Reis, André Inácio., Drechsler, Rolf., SpringerLink (Online service) |
|---|---|
| Format: | eBook |
| Language: | English |
| Published: |
Cham :
Springer,
©2018.
Cham : [2018] |
| Physical Description: |
1 online resource (236 pages) |
| Subjects: |
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| 245 | 0 | 0 | |a Advanced logic synthesis / |c André Inácio Reis, Rolf Drechsler, editors. |
| 260 | |a Cham : |b Springer, |c ©2018. | ||
| 264 | 1 | |a Cham : |b Springer, |c [2018] | |
| 264 | 4 | |c ©2018. | |
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| 505 | 0 | |a Preface; Acknowledgments; Contents; 1 EDA3.0: Implications to Logic Synthesis; 1 Introduction; 2 Warehouse-Scale Computing; 3 Scale of Applications; 4 EDA Applications; 5 EDA Applications: Analysis; 6 EDA Applications: Synthesis and Optimization; 7 Summary; References; 2 Can Parallel Programming Revolutionize EDA Tools?; 1 Introduction; 2 Abstractions for Graph Algorithms; 2.1 Operator Formulation; 2.1.1 Local View of Algorithms: Operators; 2.1.2 Global View of Algorithms: Location of Active Nodes and Ordering; 2.2 Trade-offs Between Topology-Driven and Data-Driven Algorithms. | |
| 505 | 8 | |a 3 Exploiting Parallelism in Graph Algorithms3.1 BSP-Style Semantics; 3.2 Transactional Semantics; 3.3 The Galois System; 4 Using Galois: Case Studies; 4.1 Case Study: Large-Scale Shared-Memory Machines; 4.2 Case Study: Graph Analytics; 4.3 Case Study: Subgraph Isomorphism; 4.4 Case Study: Maze Routing in FPGAs; 5 Conclusions; References; 3 Emerging Circuit Technologies: An Overview on the Next Generation of Circuits; 1 Introduction; 2 Digital Microfluidic Biochips; 2.1 Technology Platform; 2.2 Design Methods for DMFBs: Today's Solutions; 2.3 Design Methods for DMFBs: Looking Ahead. | |
| 505 | 8 | |a 3 Integrated Photonic Circuits3.1 Photonic Logic Circuit Model; 3.2 Design and Synthesis of Photonic Logic Circuits; 3.3 Challenges of Si-Photonic Integration: Thermal Issues; 4 Reversible Circuits: A Basis for Quantum Computation, Encoder Design, and More; 4.1 Circuit Model; 4.2 Application Areas; 4.2.1 Quantum Computation; 4.2.2 Encoder Design; 4.2.3 Low Power Design; 4.3 Design of Reversible Circuits; 5 Conclusions; References; 4 Physical Awareness Starting at Technology-Independent Logic Synthesis; 1 Introduction; 2 Basic Concepts in VLSI Design; 2.1 Design Constraints. | |
| 505 | 8 | |a 2.2 Sources of Delay2.2.1 Delay from Late Arrival; 2.2.2 Cell Delay Estimation; 2.2.3 Wire Delay Estimation; 2.3 Timing Closure; 2.4 Timing Budget; 2.5 Design Convergence and Delay Information Stability; 3 A Typical Flow; 3.1 Logic Synthesis Frontend; 3.2 Physical Design Backend; 3.3 Drawbacks; 4 Common Synthesis Tasks; 4.1 Gate Sizing or Repowering; 4.2 Vt Swapping; 4.3 Cell Movement; 4.4 Layer Assignment; 4.5 Buffering Long Nets; 4.6 Buffer Deletion; 4.7 Buffering Nets to Reduce Fanout; 4.8 Pin Swapping; 4.9 Cloning; 4.10 Balancing and Unbalancing of AND/OR/XOR Trees. | |
| 505 | 8 | |a 4.11 Composition/Decomposition4.12 MUX Decomposition; 4.13 Inverter Absorption (Decomposition); 4.14 Potential for Improvement; 5 Enablers of Physical Awareness Flow; 5.1 PAIGs; 5.2 KL-Cut PAIGs; 5.3 Explicit Inverters on KL-Cut PAIGs; 5.4 Different Cuts for Signal Distribution and Logic Computation; 5.5 Local SDCs; 6 Rethinking Physically Aware Flows; 6.1 Starting Point and Input; 6.2 Placement of Interface Pins; 6.3 KL-Cut Computation; 6.4 Placement of Logic Computation KL-Cuts; 6.5 Physical Design of Global Signal Distribution 1L-Cuts. | |
| 500 | |a 6.6 Generate Partial SDCs for Logic Computation KL-Cuts. | ||
| 520 | |a This book provides a single-source reference to the state-of-the-art in logic synthesis. Readers will benefit from the authors' expert perspectives on new technologies and logic synthesis, new data structures, big data and logic synthesis, and convergent logic synthesis. The authors describe techniques that will enable readers to take advantage of recent advances in big data techniques and frameworks in order to have better logic synthesis algorithms. Describes how to map logic into new post-CMOS technologies and devices; Explains how to use different types of internal data structures, such as Majority-Inverter-Graphs; Discusses how to mix logic synthesis and physical design in order to have more effective and convergent ways to perform logic synthesis integrated in a complete flow. | ||
| 650 | 0 | |a Logic design |x Data processing. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design |x Data processing. | |
| 650 | 0 | |a Computer-aided design. | |
| 650 | 6 | |a Structure logique |x Informatique. | |
| 650 | 6 | |a Conception assistée par ordinateur. | |
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| 650 | 7 | |a computer-aided design (process) |2 aat. | |
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| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design |x Data processing. |2 fast. | |
| 650 | 7 | |a Logic design |x Data processing. |2 fast. | |
| 700 | 1 | |a Reis, André Inácio. | |
| 700 | 1 | |a Drechsler, Rolf. | |
| 710 | 2 | |a SpringerLink (Online service) | |
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