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Advanced memory optimization techniques for low power embedded processors
"Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem."--Jacket.
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Corporate Author: | |
Other Authors: | |
Format: | eBook |
Language: | English |
Published: |
Dordrecht :
Springer,
©2007.
Dordrecht : [2007] |
Physical Description: |
1 online resource (xii, 188 pages) : illustrations. |
Subjects: | |
Online Access: | SpringerLink - Click here for access |
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100 | 1 | |a Verma, Manish. |0 https://id.loc.gov/authorities/names/nb2004301088. | |
245 | 1 | 0 | |a Advanced memory optimization techniques for low power embedded processors / |c by Manish Verma and Peter Marwedel. |
260 | |a Dordrecht : |b Springer, |c ©2007. | ||
264 | 1 | |a Dordrecht : |b Springer, |c [2007] | |
264 | 4 | |c ©2007. | |
300 | |a 1 online resource (xii, 188 pages) : |b illustrations. | ||
336 | |a text |b txt |2 rdacontent. | ||
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504 | |a Includes bibliographical references (pages 181-188). | ||
520 | 1 | |a "Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem."--Jacket. | |
588 | 0 | |a Print version record. | |
505 | 0 | |a Related Work -- Memory Aware Compilation and Simulation Framework -- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad Memory Hierarchy -- Non-Overlayed Scratchpad Allocation Approaches for Main/Scratchpad + Cache Memory Hierarchy -- Scratchpad Overlay Approaches for Main/Scratchpad Memory Hierarchy -- Data Partitioning and Loop Nest Splitting -- Scratchpad Sharing Strategies for Multiprocess Applications -- Conclusions and Future Directions. | |
506 | |a University staff and students only. Requires University Computer Account login off-campus. | ||
650 | 0 | |a Memory management (Computer science) |0 https://id.loc.gov/authorities/subjects/sh90003066. | |
650 | 0 | |a Memory hierarchy (Computer science) |0 https://id.loc.gov/authorities/subjects/sh88003872. | |
650 | 0 | |a Embedded computer systems. |0 https://id.loc.gov/authorities/subjects/sh87006632. | |
650 | 0 | |a Electronics. |0 https://id.loc.gov/authorities/subjects/sh85042383. | |
650 | 0 | |a Systems engineering. |0 https://id.loc.gov/authorities/subjects/sh85131750. | |
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650 | 6 | |a Hiérarchie de mémoires (Informatique) | |
650 | 6 | |a Systèmes enfouis (Informatique) | |
650 | 6 | |a Électronique. | |
650 | 6 | |a Ingénierie des systèmes. | |
650 | 6 | |a Informatique. | |
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